Digital System Test And Testable Design: Using ... -

Gate-level faults, fault collapsing, and structural modeling in Verilog.

Logic BIST basics, test pattern generation, and output response analysis. Digital System Test and Testable Design: Using ...

Scan architectures, RT-level scan design, and Boundary Scan (JTAG). The material is structured into two main parts:

The material is structured into two main parts: developing test environments and implementing testable hardware. Key Topics Covered The book by Zainalabedin Navabi (2010) is a

Verilog is used to describe the internal architectures of Built-In Self-Test (BIST) and Design for Testability (DFT) . This helps engineers evaluate hardware overhead and timing feasibility, which is critical for System-on-Chip (SoC) designs.

The book by Zainalabedin Navabi (2010) is a comprehensive guide that bridges the gap between digital design and testing methodologies. Unlike traditional texts, it uses Verilog HDL to describe and simulate test hardware, making complex concepts like fault simulation and test generation more practical and less ambiguous for designers. Core Features and Methodology

A distinguishing feature is the extensive use of the Verilog Programming Language Interface (PLI) . This allows for a mixed hardware/software environment where users can develop "virtual testers" to evaluate complex test strategies.